发明名称 Analog input and output module
摘要 <p>Provided is an analog input and output module, the module comprising a first signal processing unit configured to separate analog signal inputted from a plurality of HART transmitters from first HART data, convert the analog signal to digital data, transmit the first HART data to a second signal processing unit, and transmit second HART data received from the second signal processing unit to at least one of the plurality of HART transmitters; and the second signal processing unit configured to control the first signal processing unit and storing conversion result.</p>
申请公布号 EP2618227(A1) 申请公布日期 2013.07.24
申请号 EP20130150907 申请日期 2013.01.11
申请人 LSIS CO., LTD. 发明人 SIN, YONGGAK
分类号 G05B19/042;G05B19/05;H04L27/00 主分类号 G05B19/042
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