| 摘要 |
A pipelined analog-to-digital converter (100) is provided that has advantages of both a high input sample rate as well as low power consumption due to having all but the first pipeline stage (110) operate at a frequency that is a fraction of the input sample rate. The first stage of the pipelined ADC (110) has an internal operating frequency that is the full ADC sample rate, and samples the input signal on the same clock edge for each sample. Subsequent pipeline stages (120, 130, 140) have parallel input sampling circuitry that samples provided input signals at a reduced rate. Since the input sampling circuitry operates at a reduced frequency, power consumption is reduced by those stages. Further, by virtue of sampling the input signal on the same clock edge for each sample, frequency response image generation issues associated with ADC architectures that sample the input signal on more than one clock edge are avoided. |
