发明名称 |
Method of controlling critical dimensions of vias in a metallization system of a semiconductor device during silicon-ARC etch |
摘要 |
When forming via openings in sophisticated semiconductor devices, a silicon-containing anti-reflective coating (ARC) layer may be efficiently used for adjusting the critical dimension of the via openings by using a two-step etch process in which, in at least one of the process steps, the flow rate of a reactive gas component may be controlled to increase or reduce the resulting width of an opening in the silicon ARC layer. In this manner, the spread of critical dimensions of vias around the target value may be significantly reduced while also reducing any maintenance and rework efforts.
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申请公布号 |
US8492279(B2) |
申请公布日期 |
2013.07.23 |
申请号 |
US201113164899 |
申请日期 |
2011.06.21 |
申请人 |
RADWAN MOHAMMED;STEINMETZ JOHANN;GLOBALFOUNDRIES INC. |
发明人 |
RADWAN MOHAMMED;STEINMETZ JOHANN |
分类号 |
H01L21/311;H01L21/00;H01L21/302 |
主分类号 |
H01L21/311 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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