发明名称 |
Method and system including plural memory controllers and a memory access control bus for accessing a memory device |
摘要 |
A system and method utilize a memory device that may be accessed by a plurality of controllers or processor cores via respective ports of the memory device. Each controller may be coupled to a respective port of the memory device via a data bus. Each port of the memory device may be associated with a predefined section of memory, thereby giving each controller access to a distinct section of memory without interference from other controllers. A common command/address bus may couple the plurality of controllers to the memory device. Each controller may assert an active signal on a memory access control bus to gain access to the command/address bus to initiate a memory access. In some embodiments, a plurality of memory devices may be arranged in a memory package in a stacked die memory configuration.
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申请公布号 |
US8495310(B2) |
申请公布日期 |
2013.07.23 |
申请号 |
US20080235063 |
申请日期 |
2008.09.22 |
申请人 |
GREGORIUS PETER;HEIN THOMAS;MAIER MARTIN;RUCKERBAUER HERMANN;SCHAFFROTH THILO;SCHEDEL RALF;SPIRKL WOLFGANG;STECKER JOHANNES;QIMONDA AG |
发明人 |
GREGORIUS PETER;HEIN THOMAS;MAIER MARTIN;RUCKERBAUER HERMANN;SCHAFFROTH THILO;SCHEDEL RALF;SPIRKL WOLFGANG;STECKER JOHANNES |
分类号 |
G06F13/36;G06F13/16 |
主分类号 |
G06F13/36 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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