发明名称 |
Implementing storage adapter performance optimization with hardware chains to select performance path |
摘要 |
A method and controller for implementing storage adapter performance optimization with a predefined chain of hardware operations configured to implement a particular performance path minimizing hardware and firmware interactions, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines; and a data store configured to store a plurality of control blocks selectively arranged in one of a plurality of predefined chains. Each predefined chain defines a sequence of operations. Each control block is designed to control a hardware operation in one of the plurality of hardware engines. A resource handle structure is configured to select a predefined chain based upon a particular characteristic of the system. Each predefined chain is configured to implement a particular performance path to maximize performance.
|
申请公布号 |
US8495259(B2) |
申请公布日期 |
2013.07.23 |
申请号 |
US201113114291 |
申请日期 |
2011.05.24 |
申请人 |
BAKKE BRIAN E.;BOWLES BRIAN L.;CARNEVALE MICHAEL J.;GALBRAITH ROBERT E.;GERHARD ADRIAN C.;IYER MURALI N.;MOERTI DANIEL F.;MORAN MARK J.;RADHAKRISHNAN GOWRISANKAR;WECKWERTH RICK A.;ZIEBARTH DONALD J.;INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
BAKKE BRIAN E.;BOWLES BRIAN L.;CARNEVALE MICHAEL J.;GALBRAITH ROBERT E.;GERHARD ADRIAN C.;IYER MURALI N.;MOERTI DANIEL F.;MORAN MARK J.;RADHAKRISHNAN GOWRISANKAR;WECKWERTH RICK A.;ZIEBARTH DONALD J. |
分类号 |
G06F13/28 |
主分类号 |
G06F13/28 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|