| 摘要 |
PURPOSE: A timing generation circuit is provided to include a binary counter of three bits and a decoder circuit that is constituted of a logic element of three inputs, thereby having a small circuit scale. CONSTITUTION: A timing generation circuit comprises a binary counter of three bits, a delay circuit (201), a 3NAND circuit, an RS latch circuit (203), a 2NOR circuit, an inverter circuit (205), and a decoder circuit 401. The RS latch circuit latches a reset signal. The delay circuit delays the reset signal to reset the binary counter. The binary counter is constituted of three T-flip-flop circuits (101-103), and outputs a pulse signal of 8 bit. A D-flip-flop circuit receives an output signal of the binary counter and outputs the pulse signal of 9 bit. |
