发明名称 Method for manufacturing semiconductor substrate used for manufacturing transistor, involves utilizing substrate layer to present thermal dilation coefficient near to that of semiconductor and additional semiconductor layers
摘要 <p>The method involves forming a composite substrate layer (310) on a surface of a semiconductor layer (230). A metal contact layer is formed on the surface. The substrate layer is formed on the metal layer whose side is relative to the semiconductor layer. An additional semiconductor layer is epitaxially developed over the semiconductor layer whose side is relative to the substrate layer. The substrate layer is used to present a thermal dilation coefficient near to that of the semiconductor layer and the additional semiconductor layer. An independent claim is also included for a semiconductor structure.</p>
申请公布号 FR2985852(A1) 申请公布日期 2013.07.19
申请号 FR20120050386 申请日期 2012.01.16
申请人 SOITEC 发明人 WERKHOVEN CHRISTIAAN J.;ARENA CHANTAL
分类号 H01L21/20;B32B7/02;H01L21/71;H01L23/12 主分类号 H01L21/20
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