| 摘要 |
PROBLEM TO BE SOLVED: To provide a vector processor capable of reducing processing time by suppressing irregularities of pipeline processing and cutting wait time even when instructions having different lengths of data words are present in a mixed manner.SOLUTION: A vector processor comprises: a vector register file 401, a plurality of execution units 403 to 406 each having pipeline arithmetic units; and an instruction issue control circuit 402 that controls pipeline processing. An execution unit has a plurality of basic pipeline arithmetic units capable of processing data of the size of bit width multiplied by x of a basic bit width by combining x number of pieces of data. The instruction issue control circuit issues an instruction to execute data processing of one series by x number of execution units in executing the data processing of one series having bit width multiplied by x of the basic bit width when determining that it is appropriate to execute the data processing of one series by the x number of execution units. |
