| 摘要 |
A method and structure for mechanical self-alignment of semiconductor device features, for example multi-chip module features. Alignment of the features can be performed using mechanical alignment grooves within a layer of a first device and mechanical alignment pedestals of a second device. The alignment accuracy is limited by the patterning resolution of the semiconductor processing, which is in sub-micron scale. Flip-chip bonding can be used as the bonding process between chips to increase the alignment precision.
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