发明名称 Single clock cycle first order limited accumulator for supplying weighted corrections
摘要 A method is provided for first order accumulation in a single clock cycle. The method accepts a limited gain value and an accumulated value stored in a previous clock cycle. Using combinational logic, the limited gain value is summed with the accumulated value. If the summed value is between upper and lower limits, a non-weighted correction signal is supplied, and the summed value is the storage value. If the summed value is greater than the upper limit, a positive weighting is supplied, the (upper limit+1) is subtracted from the summed value, and the result is the storage value. If the summed value is less than the lower limit, then a negative weighting is supplied, the lower limit is subtracted from the summed value, and the result is the storage value. The storage value is loaded in memory for use as the accumulated value in the subsequent clock cycle.
申请公布号 US8489664(B2) 申请公布日期 2013.07.16
申请号 US20090399861 申请日期 2009.03.06
申请人 DO VIET LINH;FU WEI;FARHOODFAR ARASH;APPLIED MICRO CIRCUITS CORPORATION 发明人 DO VIET LINH;FU WEI;FARHOODFAR ARASH
分类号 G06F11/00 主分类号 G06F11/00
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