发明名称 |
Compact and robust level shifter layout design |
摘要 |
Method and apparatus for voltage level shifters (VLS) design in bulk CMOS technology. A multi-voltage circuit or VLS that operate with different voltage levels and that provides area and power savings for multi-bit implementation of level shifter design. A two-bit VLS to shift bits from a first voltage level logic to a second voltage level logic. The VLS formed with a first N-well in a substrate. The VLS formed with a second N-well in the substrate, adjacent to a side of the first N-well. The VLS formed with a third N-well in the substrate, adjacent to a side of the first N-well and opposite the second N-well. A first one-bit VLS circuit having a portion formed on the first N-well and a portion formed on the second N-well. A second bit VLS circuit having a portion formed on the first N-well and a portion formed on the third N-well.
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申请公布号 |
US8487658(B2) |
申请公布日期 |
2013.07.16 |
申请号 |
US201113180598 |
申请日期 |
2011.07.12 |
申请人 |
DATTA ANIMESH;GOODALL, III WILLIAM JAMES;QUALCOMM INCORPORATED |
发明人 |
DATTA ANIMESH;GOODALL, III WILLIAM JAMES |
分类号 |
H03K19/00;H01L25/00 |
主分类号 |
H03K19/00 |
代理机构 |
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代理人 |
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地址 |
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