发明名称 |
High-voltage transistor architectures, processes of forming same, and systems containing same |
摘要 |
An apparatus includes a first device with a metal gate and a drain well that experiences a series resistance that drops a drain contact voltage from 10 V to 4-6 V at a junction between the drain well and a channel under the gate. The apparatus includes an interlayer dielectric layer (ILD0) disposed above and on the drain well and a salicide drain contact in the drain well. The apparatus also includes a subsequent device that is located in a region different from the first device that operates at a voltage lower than the first device.
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申请公布号 |
US8487376(B2) |
申请公布日期 |
2013.07.16 |
申请号 |
US20100858770 |
申请日期 |
2010.08.18 |
申请人 |
HAFEZ WALID M.;JAN CHIA-HONG;RAHMAN ANISUR;INTEL CORPORATION |
发明人 |
HAFEZ WALID M.;JAN CHIA-HONG;RAHMAN ANISUR |
分类号 |
H01L29/76 |
主分类号 |
H01L29/76 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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