发明名称 Processing resource allocation within an integrated circuit supporting transaction requests of different priority levels
摘要 An integrated circuit 2 includes a plurality of transaction sources 6, 8, 10, 12, 14, 16, 18, 20 communicating via a ring-based interconnect 30 with shared caches 22, 24 each having an associated POC/POS 30, 34 and serving as a request servicing circuit. The request servicing circuits have a set of processing resources 36 that may be allocated to different transactions. These processing resources may be allocated either dynamically or statically. Static allocation can be made in dependence upon a selection algorithm. This selection algorithm may use a quality of service value/priority level as one of its input variables. A starvation ratio may also be defined such that lower priority levels are forced to be selected if they are starved of allocation for too long. A programmable mapping may be made between quality of service values and priority levels. The maximum number of processing resources allocated to each priority level may also be programmed.
申请公布号 US8490107(B2) 申请公布日期 2013.07.16
申请号 US201113137362 申请日期 2011.08.08
申请人 JALAL JAMSHED;WERKHEISER MARK DAVID;FEERO BRETT STANLEY;FILIPPO MICHAEL ALAN;PRASADH RAMAMOORTHY GURU;MANNAVA PHANINDRA KUMAR;ARM LIMITED 发明人 JALAL JAMSHED;WERKHEISER MARK DAVID;FEERO BRETT STANLEY;FILIPPO MICHAEL ALAN;PRASADH RAMAMOORTHY GURU;MANNAVA PHANINDRA KUMAR
分类号 G06F9/46;G06F15/16;G06F15/173 主分类号 G06F9/46
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