发明名称 Phase-locked loop
摘要 A phase-locked loop (PLL) including an active filter, a voltage-controlled oscillator (VCO), two phase detectors, a charge pump and a digital-to-analog converter (DAC) is provided. The VCO generates an oscillation signal according to a control signal provided at an output of the active filter. The first phase detector generates a phase difference signal according to a reference signal and a feedback signal associating with the oscillation signal. The charge pump provides a charging current to a first input of the active filter according to the phase difference. The second phase detector generates a digital reference signal according to the phase difference between the reference signal and the feedback signal. The DAC converts the digital reference signal to an analog reference voltage and provides the analog reference voltage to the second input of the active filter.
申请公布号 US8487675(B2) 申请公布日期 2013.07.16
申请号 US201113297195 申请日期 2011.11.15
申请人 HSIEH MING-YU;YEN SHIH-CHIEH;MSTAR SEMICONDUCTOR, INC. 发明人 HSIEH MING-YU;YEN SHIH-CHIEH
分类号 H03L7/06 主分类号 H03L7/06
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