发明名称 Transaction performance monitoring in a processor bus bridge
摘要 Described embodiments provide a system having a bridge for connecting two different processor buses. A process monitor within the bridge allows for measuring latency of commands issued on a first bus, passing through the bridge, and executed by clients coupled to the second bus. By using identification fields associated with the command, measuring the latency of each command begins with matching the identification field of the command to an integer. As the bridge passes acknowledgements back to the first bus, the monitoring of the command is stopped when an identification field associated with an acknowledgement matches the identification field of the command being monitored. Data collected include the minimum, maximum, total latency, and the number of commands monitored. From this data, the average latency can be easily calculated.
申请公布号 US8489792(B2) 申请公布日期 2013.07.16
申请号 US20100979665 申请日期 2010.12.28
申请人 BYRNE RICHARD J.;MASTERS DAVID S.;POLLOCK STEVEN J.;BETKER MICHAEL R.;LSI CORPORATION 发明人 BYRNE RICHARD J.;MASTERS DAVID S.;POLLOCK STEVEN J.;BETKER MICHAEL R.
分类号 G06F13/36 主分类号 G06F13/36
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