发明名称 |
Leading wiring method, leading wiring program, and leading wiring apparatus |
摘要 |
When a formed position of a via formed on a board is the same as a position of a footprint of a chip component located on the back surface of the board corresponding to an area on which a BGA is mounted, a board designing apparatus determines that the chip component and the BGA can be connected using chip on hole. When it is determined that the chip component and the BGA can be connected, the board designing apparatus carries out chip on hole by forming a via in an area of the board on which the BGA is mounted, the via leading to the footprint of the chip component located on the back surface of the board.
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申请公布号 |
US8484840(B2) |
申请公布日期 |
2013.07.16 |
申请号 |
US20100659697 |
申请日期 |
2010.03.17 |
申请人 |
SAKATA TOSHIYASU;KONNO EIICHI;FUJITSU LIMITED |
发明人 |
SAKATA TOSHIYASU;KONNO EIICHI |
分类号 |
H01R43/00;H05K13/00 |
主分类号 |
H01R43/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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