发明名称 |
Process variability tolerant programmable memory controller for a pipelined memory system |
摘要 |
In an embodiment of the invention, an integrated circuit includes a pipelined memory array and a memory control circuit. The pipelined memory array contains a plurality of memory banks. Based partially on the read access time information of a memory bank, the memory control circuit is configured to select the number of clock cycles used during read latency.
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申请公布号 |
US8488405(B2) |
申请公布日期 |
2013.07.16 |
申请号 |
US201113184873 |
申请日期 |
2011.07.18 |
申请人 |
CHACHAD ABHIJEET ASHOK;VENKATASUBRAMANIAN RAMAKRISHNAN;DAMODARAN RAGURAM;TEXAS INSTRUMENTS INCORPORATED |
发明人 |
CHACHAD ABHIJEET ASHOK;VENKATASUBRAMANIAN RAMAKRISHNAN;DAMODARAN RAGURAM |
分类号 |
G11C17/18 |
主分类号 |
G11C17/18 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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