发明名称 |
Data interface with delay locked loop for high speed digital to analog converters and analog to digital converters |
摘要 |
A system comprises a first circuit includes a data transmitter circuit that transmits digital data based on a first clock signal. A sync generator outputs a sync signal based on the first clock signal. A digital to analog converter circuit includes a data receiver circuit that latches the digital data based on a second clock signal. A digital to analog converter core receives an output of the data receiver circuit. A delay locked loop circuit determines a delay based on the second clock signal and the sync signal and outputs the first clock signal to the first circuit based on the second clock signal and the delay.
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申请公布号 |
US8488657(B2) |
申请公布日期 |
2013.07.16 |
申请号 |
US20100794152 |
申请日期 |
2010.06.04 |
申请人 |
WU MIAOCHEN;DELLACROCE BRIAN L.;MAXIM INTEGRATED PRODUCTS, INC. |
发明人 |
WU MIAOCHEN;DELLACROCE BRIAN L. |
分类号 |
H04L5/16 |
主分类号 |
H04L5/16 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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