| 摘要 |
The device has a software layer i.e. hypervisor (202), centralizing exchanges between a processor and an application (201) and implementing management mechanisms of fault tolerances. A programmable electronic component forms an interface between the processor and a memory unit e.g. synchronous dynamic RAM and a data input and output interface. One of the mechanisms is a reset function at known state of the processor, where the function is periodical with a configurable period. The mechanism is reset to the known state by a resetting signal issued by the programmable electronic component. |
