发明名称 SEMICONDUCTOR MEMORY TEST METHOD AND SEMICONDUCTOR MEMORY
摘要 PROBLEM TO BE SOLVED: To prevent a verification criteria in erase test from relaxing due to influence of a memory cell which is slow in erasing, and to prevent reliability of a semiconductor memory from degrading.SOLUTION: In a semiconductor memory test method, a first erase test is performed by applying erase pulses to a memory cell group which is included in a memory cell array and divided into a plurality of groups A, B, until a group which is determined that erase is completed is detected (Step S1). A second erase test is performed on other memory cell groups including the memory cell group on the basis of the number of erase pulses when detecting a group which is determined that erase is completed first (Step S2).
申请公布号 JP2013137845(A) 申请公布日期 2013.07.11
申请号 JP20110287935 申请日期 2011.12.28
申请人 FUJITSU SEMICONDUCTOR LTD 发明人 MORI IKU;YAGISHITA YOSHIMASA;AOKI HAJIME
分类号 G11C29/12;G11C29/44;G11C29/56 主分类号 G11C29/12
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