发明名称 Verification module apparatus to serve as a prototype for functionally debugging an electronic design that exceeds the capacity of a single FPGA
摘要 A plurality of FPGAs and off-chip storage devices provide a verification module for functionally debugging electronic circuit designs. Signal value compression circuits embedded in each FPGA conserve the limited number of pins available on each FPGA. Transmitting addresses to signal values previously stored in off-chip storage further reduce the bottlenecks in analyzing logic functionality distributed across multiple FPGAs.
申请公布号 US2013179850(A1) 申请公布日期 2013.07.11
申请号 US201213543854 申请日期 2012.07.08
申请人 CHENE MON-REN;S2C INC. 发明人 CHENE MON-REN
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
主权项
地址