发明名称 OPTIMIZED VITERBI DECODER AND GNSS RECEIVER
摘要 PROBLEM TO BE SOLVED: To handle Viterbi processing with a much lower CPU loading without significantly increasing hardware complexity.SOLUTION: A register set of a processor is arranged so as to be expanded with a plurality of phantom registers. When addressed by an instruction, the plurality of phantom registers return value calculated from registers and/or signals not explicitly addressed by the instruction.
申请公布号 JP2013138452(A) 申请公布日期 2013.07.11
申请号 JP20130015211 申请日期 2013.01.30
申请人 QUALCOMM INC 发明人 YOUNG PHIL
分类号 H03M13/41 主分类号 H03M13/41
代理机构 代理人
主权项
地址