DIGITAL ERROR CORRECTION IN AN ANALOG-TO-DIGITAL CONVERTER

摘要

An analog-to-digital converter (ADC) (15) provides digital error correction. Parallel ADC stages are synchronously clocked to convert an analog input signal (A IN) into digital words; at least one of the digital outputs (D OUT) is encoded according to an error correction code. Decision logic circuitry (24) decodes a code word comprised of the concatenation of the digital outputs from the parallel stages, to derive a digital output from which the digital output word corresponding to the analog input signal can be derived. The decision logic circuitry (24) can provide an error signal used to correct the state of one or more bits of the digital output from one of the ADC stages, for the case of a systematic code; alternatively, the decision logic circuitry can directly decode the code word to provide the digital output. The architecture may be applied to stages in a pipelined ADC.