摘要 |
In non-volatile memory devices, a write typically consists of an alternating set of pulse and verify operations. At the end of a pulse, the device must be biased properly for an accurate verify, after which the device is re-biased for the next pulse. The intervals between the pulse and verify phases are considered. For the interval after a pulse, but before establishing the verify conditions, the source, bit lines, and, optionally, the well can be equalized and then regulated at a desired DC level. After a verify phase, but before applying the biasing the memory for the next pulse, the source and bit lines can be equalized to a DC level. In some cases a non-volatile memory is programmed by an alternating set of pulses, but, for at least some pulses without any intervening verify operations. After a one pulse, but before biasing the memory for the next pulse without an intervening verify, the source and bit line levels can be left to float. |
申请人 |
SANDISK TECHNOLOGIES INC. |
发明人 |
NGUYEN, HAO THAI;LEE, JUAN CARLOS;LEE, SEUNGPIL;MATSUMOTO, MASAHIDE;PARK, JONGMIN;MUI, MAN LUNG;WANG, SUNG-EN |