Nanowire Floating Gate Transistor

摘要

A floating gate memory transistor 102, memory cell, and method of fabricating a device. The transistor includes one or more gated wires 104 substantially cylindrical, the transistor includes a first gate dielectric layer 106 at least partially covering the gated wires. The transistor further includes a plurality of gate nanocrystals 108 discontinuously arranged upon the first gate dielectric layer, the floating gate transistor also includes a second gate dielectric layer 110 covering the gate nanocrystals and the first gate dielectric layer. The crystals may be non-insulating and may be polysilicon. The charge trapping crystals store electric charge in the absence of an electric field. The transistor may further comprise an insulator layer 122 below the semiconductor layer 112 in which the wires are formed, the insulator layer having a recessed region 124 below the gate wires. The recess region may be covered by the first dielectric layer 106. The semiconductor layer may further comprise a drain pad 116 and source pad 114 which are connected by the gated wire. Silicide layers 118, 120 may be placed on the drain and source pads respectively. A gate conductor layer 128 may be placed on the second dielectric 110 layer. A planarized dielectric layer 130 may be included and a sidewall spacer 132 may separate the planarized dielectric layer and the gate conductor. The diameter of the gated wire may be less than 20nm.