发明名称 Sequential digital circuitry with test scan
摘要 A digital scan chain system having test scan has a plurality of flip-flop modules, each of the plurality of flip-flop modules having a first data bit input, a second data bit input, a test bit input, a clock input, a first data bit output, a second data bit output, and a test bit output. The test bit output of a first flip-flop module is directly connected to the test bit input of a second flip-flop module with no intervening circuitry. First and second multiplexed master/slave flip-flops are directly serially connected. A clocked latch is coupled to the output of the second multiplexed master/slave flip-flop and provides the test bit output. The clocked latch is clocked only during a test mode to save power.
申请公布号 US8484523(B2) 申请公布日期 2013.07.09
申请号 US20100729826 申请日期 2010.03.23
申请人 RAMARAJU RAVINDRARAJ;KENKARE PRASHANT U.;MUSSEMANN GARY A.;SABNIS MIHIR S.;FREESCALE SEMICONDUCTOR, INC. 发明人 RAMARAJU RAVINDRARAJ;KENKARE PRASHANT U.;MUSSEMANN GARY A.;SABNIS MIHIR S.
分类号 G01R31/28 主分类号 G01R31/28
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