发明名称 Wafer-level stack package and method of fabricating the same
摘要 A method of manufacturing a semiconductor device includes forming an integrated circuit region on a semiconductor wafer. A first metal layer pattern is formed over the integrated circuit region. A via hole is formed to extend through the first metal layer pattern and the integrated circuit region. A final metal layer pattern is formed over the first metal layer pattern and within the via hole. A plug is formed within the via hole. Thereafter, a passivation layer is formed to overlie the final metal layer pattern.
申请公布号 US8482129(B2) 申请公布日期 2013.07.09
申请号 US201113027594 申请日期 2011.02.15
申请人 LEE IN-YOUNG;LEE HO-JIN;CHUNG HYUN-SOO;CHOI JU-IL;HWANG SON-KWAN;SAMSUNG ELECTRONICS CO., LTD. 发明人 LEE IN-YOUNG;LEE HO-JIN;CHUNG HYUN-SOO;CHOI JU-IL;HWANG SON-KWAN
分类号 H01L23/48 主分类号 H01L23/48
代理机构 代理人
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