发明名称 Programmable addressing circuitry for increasing memory yield
摘要 Integrated circuits with memory elements are provided. A memory element may include a storage circuit coupled to data lines through access transistors. The access transistors may have gates that are controlled by an address signal. The address signal may be asserted during read/write operations to turn on the access transistors so that read/write data can be passed through the access transistors. The voltage level to which the address signal is raised during read/write operations may be adjusted using programmable voltage biasing circuitry. A number of integrated circuits may be tested during device characterization procedures to determine the amount by which the address signal should be adjusted using the programmable voltage biasing circuit so that the memory elements in the integrated circuits satisfy design criteria.
申请公布号 US8483006(B1) 申请公布日期 2013.07.09
申请号 US201113234990 申请日期 2011.09.16
申请人 CHOU HAO-YUAN HOWARD;ZHANG WEI;YU HAIMING;ALTERA CORPORATION 发明人 CHOU HAO-YUAN HOWARD;ZHANG WEI;YU HAIMING
分类号 G11C8/00;G11C5/14;G11C11/00 主分类号 G11C8/00
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