发明名称 |
DLL circuit, semiconductor device including the same, and data processing system |
摘要 |
To provide a DLL circuit including: a first phase determination circuit that compares phases of rising edges of an external clock and a first internal clock; a second phase determination circuit that compares phases of falling edges of the external clock and the first internal clock; an adjusting unit that adjusts positions of active edges of internal clocks based on determination results; and a control circuit that sets one of adjustment amounts of the second and third internal clocks to a larger value than the other, in response to a fact that adjustment directions of the active edges of the second and third internal clocks are mutually the same. With this arrangement, a duty can be set nearer to 50% while performing phase adjustment. Accordingly, the time required to lock the DLL circuit can be shortened.
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申请公布号 |
US8482326(B2) |
申请公布日期 |
2013.07.09 |
申请号 |
US20090646548 |
申请日期 |
2009.12.23 |
申请人 |
MIYANO KAZUTAKA;ELPIDA MEMORY, INC. |
发明人 |
MIYANO KAZUTAKA |
分类号 |
H03L7/06 |
主分类号 |
H03L7/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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