发明名称 Open loop type delay locked loop and method for operating the same
摘要 An open loop type delay locked loop includes a delay amount pulse generation unit configured to generate a delay amount pulse having a pulse width corresponding to a delay amount for delay locking a clock signal, a delay amount coding unit configured to output a code value by coding the delay amount in response to the delay amount pulse, a clock control unit configured to adjust a toggling period of the clock signal in response to a control signal, and a delay line configured to delay an adjusted clock signal outputted from the clock control unit in response to the code value.
申请公布号 US8482331(B2) 申请公布日期 2013.07.09
申请号 US20100832549 申请日期 2010.07.08
申请人 AHN SEUNG-JOON;LEE JONG-CHERN;HYNIX SEMICONDUCTOR INC. 发明人 AHN SEUNG-JOON;LEE JONG-CHERN
分类号 H03H11/26 主分类号 H03H11/26
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