发明名称 Logical repartitioning in design compiler
摘要 During a pop phase of hierarchical repartitioning of an IC design, all cells within a current hierarchy may be identified, the list of cells may be ungrouped to dissolve the current hierarchy, one or more specified cells may be removed from the list of cells, where the specified one or more cells are to be moved to a different hierarchy, and the new list of cells without the specified one or more cells may be re-grouped, to re-form the previously dissolved hierarchy. During a push phase of the hierarchical repartitioning, all cells within the next lower-level hierarchy may be identified, the identified list of cells may be ungrouped to dissolve that hierarchy, the specified one or more cells may be added to the identified list of cells, and the new list of cells that includes the specified one or more cells may be grouped to reform the previously dissolved hierarchy.
申请公布号 US8484589(B2) 申请公布日期 2013.07.09
申请号 US201113283665 申请日期 2011.10.28
申请人 KENNEY ROBERT D.;SALEH HANI HASAN MUSTAFA;RAMACHANDRA SREEVATHSA;APPLE INC. 发明人 KENNEY ROBERT D.;SALEH HANI HASAN MUSTAFA;RAMACHANDRA SREEVATHSA
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
主权项
地址