| 摘要 |
PURPOSE: Quantifying read and write margins of memory bit cells is provided to perform separate memory read margin and memory write margin screening without transforming a self-test circuit built in a memory. CONSTITUTION: A bit cell (602) is composed of cross-combined CMOS inverters. Each inverter is combined with each bit line through a corresponding access transistor. A word line driver (622) has an output terminal combined with a word line. A selector (624) has a first input terminal combined with a first power supply node, a second input terminal combined with a second power supply node, a third input terminal combined with a first control signal source, and an output terminal combined with a supply rail of the word line driver. A voltage regulator (626) has a first input terminal combined with a third power supply node, a second input terminal combined with a second control signal source, and an output terminal combined with the second power supply node. [Reference numerals] (602) Bit cell; (AA) In a test mode : VDD = VDDW in write, VDDR in read; (BB) In a normal operation : VDD = VDDW = VDDA |
