| 摘要 |
The present disclosure discloses a metal layout of an integrated power transistor. The metal layout comprises a 1st metal layer, a 2nd metal layer, and a 3rd metal layer. The metal layout couples the 1st metal layer to the 2nd metal layer through vias, and couples the 2nd metal layer to the 3rd metal layer through super vias. By such interconnection, the metallization resistance is highly reduced by using thick 2nd and 3rd metal layers.
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