| 摘要 |
A parallel test circuit of a semiconductor memory apparatus includes a memory bank which includes first and second sub banks having test global lines, respectively, and sharing a global line connected to each of the first and second sub banks. When a read command is applied during a test mode, the parallel test circuit compares data loaded in the global line to data loaded in the test global line of the second sub bank to attain a comparison result, compresses the comparison result to attain a compression signal, and outputs the compression signal as a test output signal to a pad. |
