发明名称 |
PROCESSORS HAVING FULLY-CONNECTED INTERCONNECTS SHARED BY VECTOR CONFLICT INSTRUCTIONS AND PERMUTE INSTRUCTIONS |
摘要 |
An apparatus includes a decode unit to decode a permute instruction and a vector conflict instruction. A vector execution unit is coupled with the decode unit and includes a fully-connected interconnect. The fully-connected interconnect has at least four inputs to receive at least four corresponding data elements of at least one source vector. The fully-connected interconnect has at least four outputs. Each of the at least four inputs is coupled with each of the at least four outputs. The execution unit also includes a permute instruction execution logic coupled with the at least four outputs and operable to store a first vector result in response to the permute instruction. The execution unit also includes a vector conflict instruction execution logic coupled with the at least four outputs and operable to store a second vector result in a destination storage location in response to the vector conflict instruction. |
申请公布号 |
WO2013101132(A1) |
申请公布日期 |
2013.07.04 |
申请号 |
WO2011US67982 |
申请日期 |
2011.12.29 |
申请人 |
INTEL CORPORATION;FORSYTH, ANDREW THOMAS;BRADFORD, DENNIS R. |
发明人 |
FORSYTH, ANDREW THOMAS;BRADFORD, DENNIS R. |
分类号 |
G06F13/14;G06F9/30;G06F9/305 |
主分类号 |
G06F13/14 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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