发明名称 FAILURE ANALYSIS APPARATUS, METHOD AND PROGRAM
摘要 PROBLEM TO BE SOLVED: To improve analysis accuracy of failure analysis.SOLUTION: A detection example 3 using a circuit graph is shown in (D). The detection example 3 is a detection example which uses past failure occurrence rates. More specifically, a failure analysis method in the detection example 3 includes: dividing a chip in a mesh state and using a failure map recording the failure occurrence rate for each region; mapping portions that are laid out in a region R having the high failure occurrence rate of the failure map M in a circuit graph; and thereby detecting links Lx, La, Lb, and Lc in the region R as failure candidates among a group of links in a chain line back-traced from nodes Na and Nb.
申请公布号 JP2013130553(A) 申请公布日期 2013.07.04
申请号 JP20110282335 申请日期 2011.12.22
申请人 FUJITSU LTD 发明人 NITTA IZUMI
分类号 G01R31/28 主分类号 G01R31/28
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