| 发明名称 |
CACHE MEMORY STAGED REOPEN |
| 摘要 |
<p>An apparatus is described. The apparatus includes a cache memory having two or more memory blocks and a central processing unit (CPU), coupled to the cache memory, to open a first memory block within the cache memory upon exiting from a low power state.</p> |
| 申请公布号 |
WO2013100940(A1) |
申请公布日期 |
2013.07.04 |
| 申请号 |
WO2011US67497 |
申请日期 |
2011.12.28 |
| 申请人 |
INTEL CORPORATION;SORANI, IRIS;NOVAKOVSKY, LARISA;NUZMAN, JOSEPH |
发明人 |
SORANI, IRIS;NOVAKOVSKY, LARISA;NUZMAN, JOSEPH |
| 分类号 |
G06F12/08;G06F1/32;G06F13/14 |
主分类号 |
G06F12/08 |
| 代理机构 |
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