| 摘要 |
According to the embodiments, a memory system includes a plurality of memory chips, I/O signal lines, CE signal lines, and a control unit. The plurality of memory chips is divided to a plurality of first groups. The first plurality of memory chips for each first group is divided to a plurality of second groups. Each of the I/O signal lines is commonly connected to the memory chips for each first group. Each of the CE lines is commonly connected to the memory chips for each second group. The control unit specifies one of the second groups using the CE signal line, and transmits a reset command to one of the I/O signal lines which is connected to the specified second group, at activation. Each of the memory chips belonging to the specified second group executes reset processing at respective timings after receiving the reset command.
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