发明名称 CACHE COPROCESSING UNIT
摘要 <p>A cache coprocessing unit in a computing system includes a cache array to store data, a hardware decode unit to decode instructions that are offloaded from being executed by an execution cluster of the computing system to reduce load and store operations between the execution cluster and the cache coprocessing unit, and a set of one or more operation units to perform operations on the cache array according to the decoded instructions.</p>
申请公布号 WO2013101216(A1) 申请公布日期 2013.07.04
申请号 WO2011US68213 申请日期 2011.12.30
申请人 INTEL CORPORATION;JHA, ASHISH 发明人 JHA, ASHISH
分类号 G06F9/30;G06F12/08 主分类号 G06F9/30
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