发明名称 |
METHOD OF FORMING VIA HOLE IN CIRCUIT BOARD |
摘要 |
A method of forming a via hole in a circuit board including an insulating layer and a metal layer disposed on each of top and bottom surfaces of the insulating layer, the method including: selectively removing a portion of each of the metal layers where the via hole is to be formed thereby exposing the insulating layer; and removing the exposed insulating layer, wherein the removing of the exposed insulating layer includes chemically swelling the exposed insulating layer and removing the swollen insulating layer.
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申请公布号 |
US2013168349(A1) |
申请公布日期 |
2013.07.04 |
申请号 |
US201213727038 |
申请日期 |
2012.12.26 |
申请人 |
SAMSUNG TECHWIN CO., LTD.;SAMSUNG TECHWIN CO., LTD. |
发明人 |
KWON SOON CHUL;LEE SANG MIN |
分类号 |
H05K3/22 |
主分类号 |
H05K3/22 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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