| 摘要 |
When a state in which respective instruction flows corresponding to a memory copy instruction specifying data copy or move between memory addresses are executed with a maximum specifiable data transfer volume is specified by +P_MVC_256_1ST signal, 1-bit latch 703 holds the state during the period of multi-flow expansion specified by +D_MF_TGR signal. An AND circuit 705 ANDs an output signal of the 1-bit latch 703 and +P_EAG_VALID signal indicating the execution timing of the respective instruction flows, and outputs a prefetch request signal +P_PREFETCH_REQUEST via an OR circuit 706 every time when the instruction flow is issued. |
