| 摘要 |
An interrupt management apparatus 200 for managing interrupt events generated by peripheral devices and computing modules, comprising: an event decoder 210 for receiving and decoding interrupt signals from interrupt sources to produce control data relating to an interrupt event; a sequence memory 220 for storing sequences, a sequence comprising steps for handling interrupt events; and sequencers 230 for interpreting steps of sequences stored in sequence memory 220, the sequencers 230 being arranged to receive said control data from decoder 210. The event decoder implements a mapping between received interrupt signals and stored sequences, while the sequencer further comprises access controller 238 for controlling access to the sequence memory and data bus 250. The steps can comprise: variable storage, loop or branch command, arithmetic computation, further interrupt signal to be sent to a processing unit. A plurality of sequencers can be provided to interpret sequences in parallel. The apparatus 200 manages said interrupt events without assistance from a central processing unit. The apparatus can be comprised in telecommunication modules such as modems and coupled to a power domain including a Fast Frequency Transform (FFT) and a detection module. The apparatus can be provided by a single chip, chipset, ASIC, or FPGA. |
