| 摘要 |
The invention relates to a boundary scan chain (175, figure 1) for stacked memory (120, figure 1). An embodiment of a memory device includes a system element (110, figure 1) and a memory stack (120 figure 1) including one or more memory die layers (125, 135, 145, 155 figure 1), each memory die layer including input-output (I/O) cells and a boundary scan chain (175, figure 1) for the I/O cells 205. A boundary scan chain of a memory die layer includes a scan chain portion for each of the I/O cells 205, the scan chain portion for an I/O cell including a first scan logic multiplexer 214 a scan logic latch 216, an input of the scan logic latch being coupled with an output of the first scan logic multiplexer, and a decoder 250 to provide command signals to the boundary scan chain. The memory stack includes a plurality of through silicon vias (TSVs) to carry signals through the memory device, the TSVs including connections for scan testing using the boundary scan chain of each memory die layer. The invention also includes a method of operating the scan. The invention further comprises a system including a processor to process data for the system, a transmitter to transmit data a receiver to receive data or both via an omni-directional antenna. The system also includes a computer readable storage medium stored data thereon, the data representing sequences of instructions. |
