| 摘要 |
A system, circuit, and device for asynchronously scan capturing multi-clock domains. A system includes a shift register configured to process select data for selecting a clock domain at a time in response to a scan capture pulse and a one-hot n-to-2n decoder connected to the shift register and configured to generate one-hot code based on the select data. The system also includes integrated clock gating cells connected to the one-hot n-to-2n decoder, where the scan capture pulse is applied to each one of the integrated clock gating cells, and where only one of the integrated clock gating cells associated with the clock domain is enabled when the one-hot code is processed by the integrated clock gating cells. Further, the system includes multiplexers connected to the integrated clock gating cells, where the multiplexers are configured to forward the scan capture pulse to the clock domain.
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