| 摘要 |
A signal processing circuit is provided that includes a CMOS bridge rectifier circuit having a first input terminal and a second input terminal for receiving a rectangular wave form that includes a data sequence. A first output terminal and a second output terminal provides a rectified dc output voltage. A first data output terminal is connected to one of the first and the second input terminals, and a second data output terminal is connected to one of the first and the second output terminals, wherein the data output terminals provide an output signal representative of the data sequence. A substantially resistive load may be operatively coupled between the first and second voltage output terminals, the resistive load without a discrete parallel capacitor.
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