FILTERING CIRCUIT, PHASE IDENTITY DETERMINATION CIRCUIT AND DELAY LOCK LOOP

摘要

PURPOSE: A filtering circuit, a phase identity determination circuit, and a delay lock loop are provided to reduce power consumption by changing an operation clock of a filter according to an operation condition. CONSTITUTION: A filtering circuit includes a clock selection unit (310) and a clock divider (330). The clock selection unit delivers a first clock (CLK1) or a second clock (CLK2) whose frequency is lower than that of the first clock to an operation clock (CLKA) in response to a frequency signal. A filter synchronizes the operation clock and generates a filter signal by filtering an input signal. [Reference numerals] (331) T flip-flop; (AA) Filter; (BB) Clock selection unit