发明名称 |
AN ASYMMETRIC PERFORMANCE MULTICORE ARCHITECTURE WITH SAME INSTRUCTION SET ARCHITECTURE (ISA) |
摘要 |
A method is described that entails operating enabled cores of a multi-core processor such that both cores support respective software routines with a same instruction set, a first core being higher performance and consuming more power than a second core under a same set of applied supply voltage and operating frequency. |
申请公布号 |
WO2013095944(A1) |
申请公布日期 |
2013.06.27 |
申请号 |
WO2012US68274 |
申请日期 |
2012.12.06 |
申请人 |
INTEL CORPORATION |
发明人 |
VARGHESE, GEORGE;JAHAGIRDAR, SANJEEV S.;MARR, DEBORAH T. |
分类号 |
G06F15/80;G06F1/32;G06F13/14 |
主分类号 |
G06F15/80 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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