发明名称 REDUNDANT REGISTER IN MULTI-PHASE CODE
摘要 FIELD: information technologies.SUBSTANCE: redundant register comprising memory cells of information signals Ra, from which by signals from a control bus the data arrives into a block of correction, besides, the register includes memory cells of reference signals Rx and blocks of error correction, inputs of which are connected with the block of correction and with elements of memory cells Rx, Ra, at the same time outputs of error correction blocks in the reference part X'(x', x', x') and information part A'(a'?a') are connected with elements of the memory cells Rx, Ra accordingly, and are the outputs of the register.EFFECT: higher reliability and noise immunity of electric drives with digital control due to higher validity of functioning of devices comprising memory cells.6 dwg
申请公布号 RU2486611(C1) 申请公布日期 2013.06.27
申请号 RU20110145988 申请日期 2011.11.11
申请人 OTKRYTOE AKTSIONERNOE OBSHCHESTVO "NAUCHNO-PROIZVODSTVENNYJ TSENTR "POLJUS" 发明人 BELITSKAJA LILIJA ANATOL'EVNA;GOGOLIN VIKTOR ALEKSANDROVICH
分类号 G11C19/00;G11C11/16 主分类号 G11C19/00
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