| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of performing a test in a state in which a plurality of defective addresses that have been detected by a plurality of tests are relieved in a pseudo manner while suppressing an increase in a circuit area. <P>SOLUTION: The semiconductor device includes: a third circuit 105 for outputting first and second fail latch signals according to changes in a fail signal in each time period of first and second test cycles and keeping the output first and second fail latch signals until the exit of a test mode; a fourth circuit 106 for latching addresses on the basis of the first and second fail latch signals and outputting the latched addresses as first and second fail addresses; a fifth circuit 107 for outputting the first and second fail addresses as first and second redundant addresses in the test mode; a sixth circuit 108 for outputting the first and second fail latch signals as first and second enable signals in the test mode; and a redundancy determination circuit 109 for generating a redundancy determination signal according to the address, the first and second redundant addresses and the first and second enable signals. <P>COPYRIGHT: (C)2013,JPO&INPIT |
