| 摘要 |
There is described a DC-DC converter having a Step-Up stage (10) supplying a Step-Down stage (20). A common Step-Down controller is designed and configured such that a single reference voltage (VREF) is compared to the output voltage (VOUT_SD) of the Step-Down stage by a single comparator (61), producing a single error signal (VERROR). The error signal is then compared by comparators (62) and (63) to the two different saw signals (SAW1) and (SAW2) respectively in order to generate first and second pulse-width modulated signals (PWM_SU) and (PWW_SD) respectively that are inputted a the control unit (65) of the controller which, in turn, generates a first pair of control signals (phi1,phi2) and a second pair of control signals (phi3,phi4), which control switching of the Step-Up stage (10) supplying a Step-Down stage (20). |
